1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) oscillation circuit, and, more particularly, to a PLL oscillation circuit which prevents the phase noise characteristic and spurious characteristic of a VCO (Voltage Controlled Oscillator) output from being degraded.
2. Description of the Related Art
A conventional digitally controlled PLL oscillation circuit will be described referring to FIG. 10. FIG. 10 is a configuration block diagram of the conventional digitally controlled PLL oscillation circuit.
As shown in FIG. 10, the conventional digitally controlled PLL oscillation circuit has a VCO 1, a frequency divider 2, a reference oscillation circuit 3, an A/D (Analogue/Digital) converter 4, a phase comparator 5, a digital filter 6, a D/A (Digital/Analogue) converter 7, and an analog filter 8.
The VCO 1 is a voltage controlled oscillator that generates a desired frequency Fout in response to an input from the analog filter 8 as a control voltage.
The frequency divider 2 divides the oscillation frequency Fout generated by the VCO 1 to 1/N, and sends the resultant frequency to the A/D converter 4.
The reference oscillation circuit 3 generates a reference signal (reference clock) Fref.
The A/D converter 4 converts an analog signal from the frequency divider 2 to a digital signal according to the reference clock supplied from the reference oscillation circuit 3.
The phase comparator 5 compares the phase of the digital signal from the A/D converter 4 with the phase of the reference signal from the reference oscillation circuit 3, and outputs a phase difference signal.
The digital filter 6 filters the phase difference signal from the phase comparator 5.
The D/A converter 7 converts the digital signal from the digital filter 6 to an analog signal according to the reference clock supplied from the reference oscillation circuit 3.
The analog filter 8 smooths the analog signal from the D/A converter 7, and outputs the analog signal as a control voltage to the VCO 1.
Japanese Patent Application Laid-Open No. 2004-253945 discloses a related art relating to a PLL circuit. The related art is a signal phase synchronization apparatus that stably extracts a clock with a less frequency variation from a PLL circuit using a bandpass filter (XBPF) comprising a crystal oscillator.
The related art is premised on an analogously controlled PLL circuit and configured to allow a reproduction signal input to the phase comparator to pass the XBPF.
In the PLL oscillation circuit, the reference signal Fref is used in each of the A/D converter 4, the phase comparator 5 and the D/A converter 7. Because the reference signal Fref significantly influences the PLL performance, the reference signal Fref should desirably be stable free of noise, jitter or a spurious wave.
If the reference signal contains noise, jitter or a spurious wave, however, the phase noise characteristic and spurious characteristic of the output Fout of the VCO 1 would be degraded.
Particularly, the A/D converter 4 generates a digital signal to be subjected to phase comparison, and is likely to be influenced by the reference signal Fref, thereby significantly influencing the whole PLL oscillation circuit.